The present disclosure relates generally to semiconductor processing, and more particularly to a method for removing photoresist residue from a surface of a semiconductor wafer.
Semiconductor device geometries have dramatically decreased in size since such devices were introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.13 μm and even 90 nm feature sizes and smaller. In the process of reducing the sizes of integrated circuits, it has been necessary to employ conductive materials having low resistivity and insulating materials having low dielectric constants to reduce the capacitive coupling between adjacent metal lines.
A damascene process is often used to form metal interconnections within integrated circuits. The process involves creating interconnect lines by first etching a trench or canal in a planar low-k dielectric layer and then filling that trench with metal, such as copper. In dual damascene processing, a second level is provided where a series of holes (e.g., contacts or vias) are etched and filled in addition to the trench. These processes are repeated many times over in order to meet the requirements for multi-level high density wiring formation. However, it has been shown that oxygen-containing plasmas in an ashing step to remove a photoresist after etching cause the low-k dielectric layer to degrade and increase the k value of the dielectric layer. What is needed is a simple and cost-effective method for stripping the photoresist without damaging the dielectric layer.